SSN engineers are proficient with the full range of industry-standard Electronic Design Automation tools — from simulation to signoff.

Simulation & Verification Platforms

• Cadence Xcelium — primary simulation engine; SSN engineers use Xcelium’s advanced coverage, assertion, and UVM debug features daily.
• Synopsys VCS — constraint-random simulation, formal sign-off, and coverage closure.
• Mentor / Siemens Questa — UVM simulation, mixed-signal verification, and formal property checking.

Formal Verification

• Cadence JasperGold — property checking, unreachability analysis, connectivity checking.
• Synopsys VC Formal — App-based formal: FPV, coverage, security, CDC formal.
• Mentor Questa Formal — SVA property verification and X-propagation formal analysis.

Coverage & Debug

• Cadence IMC (Integrated Metrics Center) — coverage merging, grading, and reporting across regression runs.
• Synopsys Verdi — waveform analysis, SystemVerilog/UVM-aware debug, assertion failure navigation.
• Cadence SimVision — protocol-aware waveform viewer with FSM and memory panel views.

Synthesis & Physical Design

• Synopsys Design Compiler / Fusion Compiler — RTL synthesis and netlist generation.
• Cadence Genus / Innovus — synthesis and placement-and-route.
• Synopsys SpyGlass — CDC/RDC/lint analysis on RTL and gate-level netlists.

Test Plan & Project Management

• Cadence vManager — verification test plan management, coverage dashboard, and sign-off tracking.
• Mentor Questa Verification Management — test plan to coverage closure management.
• JIRA / Confluence — bug tracking, test plan documentation, and team collaboration.