The Verification Challenge

The client was taping out a high-performance datacenter PCIe switch SOC implementing a Gen4 Root Complex with 16-lane operation. The design incorporated a multi-layer AXI4 interconnect, a 32-channel scatter-gather DMA engine, and an advanced error recovery subsystem. The LTSSM (Link Training and Status State Machine) alone had over 2,000 reachable states. First-time silicon failure would have cost an estimated $1.2M in re-spin costs plus 6 months of schedule.

SSN Methodology & Solution

SSN deployed a 4-engineer team with deep PCIe and UVM expertise. The approach:

• UVM Environment Build: Constructed a hierarchical UVM environment with a PCIe TLP generator, data-link layer DLLP agent, LTSSM controller, and AXI4 host agent. The environment included 47 UVM sequences covering nominal operation, error injection, and link recovery.
• Protocol VIP Integration: Integrated Cadence VIP for PCIe Gen4 as a reference master. All TLP transactions from the DUT were compared cycle-accurately against the VIP reference model.
• LTSSM Coverage Model: Defined 380 functional coverage bins covering every LTSSM transition, timeout scenario, and recovery state. Achieving 100% LTSSM coverage required 6 weeks of constrained-random simulation with targeted transition forcing.
• Error Injection Suite: Implemented systematic error injection including: TLP sequence number errors, CRC errors in data payloads, DLLP NAK sequences, flow credit exhaustion, malformed TLP headers, and unexpected Completion Timeout scenarios.
• AXI-to-PCIe Bridge Verification: Verified the AXI4 master-to-TLP translation logic with 23 cross-coverage bins correlating AXI burst type, burst length, and PCIe TLP type.
• DMA Scatter-Gather Verification: Built a C-model reference DMA engine in SystemVerilog DPI-C, enabling scoreboard comparison of every DMA descriptor chain execution.