The Verification Challenge

The client’s SOC integrated an ARM Cortex-A55 quad-core cluster, a multi-layer AXI4 Network-on-Chip, 14 peripheral blocks on an APB bus matrix, an AHB subsystem for legacy IP, a PCIe Gen3 Endpoint, a 1G Ethernet MAC, and an on-chip SRAM subsystem with ECC. The full-chip UVM environment required coordinated stimulus across all these interfaces simultaneously, with a scoreboard that could track transactions across protocol boundaries (AXI to APB bridges, AXI to PCIe translation). The sheer scale of the environment — 47 UVM agents, 6 scoreboards, 12 virtual sequences — was the primary technical challenge.

SSN Methodology & Solution

• Environment Architecture: SSN’s lead architect designed a three-tier environment: chip-level virtual sequences orchestrated agent-level sequences which drove protocol-specific agents. TLM FIFOs and analysis ports wired the full observation fabric.
• AXI NoC Stress Testing: Deployed 8 concurrent AXI masters with randomized priority, burst size, and address spread to stress the NoC arbitration logic. 34 cross-coverage bins verified QoS behavior under maximum contention.
• APB Bus Matrix Coverage: All 14 peripheral register maps verified via UVM RAL. APB bus matrix arbitration verified with concurrent access from 3 AXI-to-APB bridge masters.
• AHB-to-APB Bridge: Verified all AHB-to-APB bridge pipelining scenarios including back-to-back transfers, SPLIT response handling, and address boundary cases.
• Cross-Protocol Scoreboard: The central scoreboard tracked transactions from AXI master initiation through NoC routing, bridge translation, and peripheral completion — flagging any lost, duplicated, or corrupted transactions.
• PCIe Endpoint Integration: Verified PCIe EP within the full-chip context including outbound DMA through the AXI NoC, BAR decoding to peripheral address space, and MSI-X interrupt delivery to the Cortex-A55.

Results