The Verification Challenge

This was SSN’s most complex engagement to date. The 5G baseband SOC implemented 3GPP NR Layer-1 signal processing (FFT/iFFT, channel estimation, LDPC encode/decode) in hardware accelerators, connected via AXI4-Stream data planes. The fronthaul interface used CPRI 10.0 at 24.33 Gbps. ADC and DAC interfaces used JESD204B at 12.8 Gbps per lane. The PCIe Gen4 x8 backhaul connected to the host processor. Verifying correctness of the L1 data path from CPRI input to PCIe output — including all signal processing accuracy requirements — demanded a multi-domain verification strategy spanning bit-accurate algorithmic simulation and protocol-level testbench work.

SSN Methodology & Solution

• Bit-Accurate Reference Models: Developed 3GPP-conformant reference models in SystemVerilog DPI-C for FFT, channel estimation, and LDPC coding. Models were calibrated against MATLAB reference implementations provided by the client.
• CPRI 10.0 UVM Agent: Built a custom CPRI 10.0 UVM agent (no commercial VIP available) implementing hyperframe synchronization, I/Q sample mapping, vendor-specific region handling, and link-layer error injection.
• JESD204B Agent: Integrated Analog Devices JESD204B simulation model for ADC/DAC interface verification; wrote custom UVM wrapper for seamless scoreboard integration.
• End-to-End Data Path Scoreboard: A master scoreboard tracked I/Q samples from CPRI ingress through ADC capture, baseband processing, LDPC encoding, and PCIe egress — comparing against the C-model at every pipeline stage.
• L1 Algorithmic Coverage: Defined coverage bins for all 3GPP NR numerology configurations (subcarrier spacings 15/30/60/120 kHz), OFDM symbol count per slot, and LDPC base graph selection.
• Stress and Corner Testing: Simultaneous injection of CPRI link errors, JESD204B lane errors, and PCIe flow control stalls to verify graceful degradation and alarm reporting.

Results