The Verification Challenge

The client was developing a 28Gbps SerDes digital controller IP for use in automotive-grade SOCs requiring AEC-Q100 Grade 1 reliability. The digital controller managed CDR lock sequences, adaptive equalization, CTLE/DFE coefficient optimization, lane power management, and BIST (Built-In Self-Test) operations. The verification challenge was two-fold: verifying the complex analog-behavioral interactions via Verilog-AMS mixed-signal simulation, and achieving the comprehensive functional coverage required for ISO 26262 ASIL-B compliance.

SSN Methodology & Solution

• Mixed-Signal Testbench: Built a UVM testbench integrating the digital controller RTL with a Verilog-AMS analog model of the PLL, CDR, CTLE, and DFE blocks. Enabled realistic bring-up sequence simulation.
• CDR Lock Coverage: Defined 78 coverage bins for CDR lock state machine transitions, including lock/unlock hysteresis, frequency offset tolerance, and clock recovery under jitter injection.
• Equalization Adaptation Coverage: Verified CTLE tap coefficient adaptation across 15 channel loss profiles. DFE tap coefficient convergence verified for worst-case ISI channels.
• BIST Verification: Complete functional verification of loopback BIST including PRBS7/15/31 pattern generation, error counting, and BER estimation logic.
• Power Management: Verified all power-down and power-up sequences, including lane sleep/wake handshake with the MAC layer, and guaranteed no data corruption on wake events.

Results