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NEW QUESTION: 1
Which three guidelines and limitations of policy-based routing are true? (Choose three.)
A. A policy-based routing route map can have multiple match or set statements per route- map statement.
B. An ACL used in a policy-based routing route map cannot include a deny statement.
C. The same route map can be shared among different interfaces for policy-based routing as long as the interfaces belong to the same VRF instance.
D. A match command can refer to more than one ACL in a route map used for policy-based routing.
E. Policy-based routing and WCCPv2 are not supported on the same interface if bank chaining is disabled.
F. Setting a tunnel interface or an IP address via a tunnel interface as a next hop in a policy-based routing policy is not supported.
Answer: B,C,F

NEW QUESTION: 2
Match each HPE solution to its optimal use case.

Answer:
Explanation:

Explanation

NEW QUESTION: 3
Scopia and Avaya Aura Conferencing have been set up to interoperate. What type of signaling is used in the connection between Scopia Management and Session Manager?
A. ISDN
B. Scopia
C. SIP
D. H.323
Answer: C
Explanation:
Explanation/Reference:
Reference: https://downloads.avaya.com/css/P8/documents/100180521 (p.28)

NEW QUESTION: 4
The design of the z13 Systems processor unit (PU) chip has been enhanced over the zEC12.
Which of the following characterizes the improvement?
A. Up to six active cores per chip on z13 compared to four active cores on zEC12.
B. Larger cache level sizes on z13 compared to zEC12.
C. Improved cryptographic and compression engine shared over all cores.
D. Faster processor cycle time on z13 (5.5 GHz instead of 5.0 GHz on zEC12).
Answer: B
Explanation:
Contributing to the additional capacity on the z13 and z13s are numerous improvements in processor chip design, including new instructions, multithreading, and redesigned and larger caches.
Z13 processor:
* L1 cache
9 6 KB I-L1
1 28 KB D-L1 per core
* L2 cache
2 MB I-L2
2 MB D-L2 per core
L3 cache 64 MB shared
zEC12 processor:
L1 cache64+96 KB/core
L2 cache1+1 MB/core
L3 cache48 MB/chip
References:
https://en.wikipedia.org/wiki/IBM_zEC12_(microprocessor)
https://en.wikipedia.org/wiki/IBM_z13_(microprocessor)